There were whole CHAPTERS on that shit lol, bored me 2 death, i just stopped showing up and gettin 90% + on tests from home
lol 5.50am 7.30pm here
lol 5.50am 7.30pm here
Apparently Aussieland is on the opposite side of the globe where I live.Afroman.exe wrote:
There were whole CHAPTERS on that shit lol, bored me 2 death, i just stopped showing up and gettin 90% + on tests from home
lol 5.50am 7.30pm here
Google is your friend.
lol apparentlyNoobpatty wrote:
Apparently Aussieland is on the opposite side of the globe where I live.Afroman.exe wrote:
There were whole CHAPTERS on that shit lol, bored me 2 death, i just stopped showing up and gettin 90% + on tests from home
lol 5.50am 7.30pm here
took cisco 1 and 2 last year, aced everyone of those testshaffeysucks wrote:
hahahaha gl, hf. cisco is a BITCH.CosmoKramer wrote:
cisco test
i'm taking cisco 3 right now. be ready to fail your next test.
....You think I didn't try?killer21 wrote:
Google is your friend.
I guess. I did a quick search and found all three of your answers, although, I knew two of your questions off the top of my dome. But yea, I understand.Noobpatty wrote:
....You think I didn't try?
1. As already noted, the answer is RISC and CISC.
2. As already noted, SRAM is the answer.
2. As already noted, SRAM is the answer.
3. As already noted, the answer is seven.As the x86 CPU architecture reached clock speeds of 20 MHz and above in the 386, small amounts of fast cache memory began to be included in the architecture to boost performance. This was because the DRAM used for main memory had significant latency, up to 120ns, as well as refresh cycles. The cache was constructed from more expensive, yet significantly faster, SRAM, which at the time had latencies around 10ns. The early caches were external to the processor and typically located on the motherboard in the form of 8 or 9 DIP memory chips placed in sockets to enable the cache as an optional extra or upgrade feature.